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Silicon Labs /SiM3_NRND /SIM3U164_B /PBCFG_0 /XBAR1

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Interpret as XBAR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NONE)SSG0EN 0 (DISABLED)CMP0SEN 0 (DISABLED)CMP1SEN 0 (DISABLED)SPI1EN 0 (DISABLED)SPI1NSSEN 0 (DISABLED)RTC0EN 0 (DISABLED)SPI2EN 0 (DISABLED)SPI2NSSEN 0 (DISABLED)USART1EN 0 (DISABLED)USART1FCEN 0 (DISABLED)USART1CEN 0 (DISABLED)UART0EN 0 (DISABLED)UART0FCEN 0 (DISABLED)I2S0TXEN 0 (DISABLED)I2C0EN 0 (DISABLED)UART1EN 0 (DISABLED)I2S0RXEN 0 (DISABLED)LPT0OEN 0 (DISABLED)I2C1EN 0 (DISABLED)KILLHDEN 0 (DISABLED)XBAR1EN

SPI2EN=DISABLED, SSG0EN=NONE, SPI2NSSEN=DISABLED, UART0FCEN=DISABLED, UART0EN=DISABLED, SPI1EN=DISABLED, USART1EN=DISABLED, LPT0OEN=DISABLED, UART1EN=DISABLED, XBAR1EN=DISABLED, I2S0RXEN=DISABLED, I2S0TXEN=DISABLED, USART1CEN=DISABLED, USART1FCEN=DISABLED, I2C1EN=DISABLED, SPI1NSSEN=DISABLED, CMP0SEN=DISABLED, KILLHDEN=DISABLED, I2C0EN=DISABLED, RTC0EN=DISABLED, CMP1SEN=DISABLED

Description

Crossbar 1 Control

Fields

SSG0EN

SSG0 Enable.

0 (NONE): Disable all SSG0 channels on Crossbar 1.

1 (EX0): Enable SSG0 EX0 on Crossbar 1.

2 (EX0_1): Enable SSG0 EX0 and EX1 on Crossbar 1.

3 (EX0_3): Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1.
CMP0SEN

Comparator 0 Synchronous Output (CMP0S) Enable.

0 (DISABLED): Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.

1 (ENABLED): Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.
CMP1SEN

Comparator 1 Synchronous Output (CMP1S) Enable.

0 (DISABLED): Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.

1 (ENABLED): Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.
SPI1EN

SPI1 Enable.

0 (DISABLED): Disable SPI1 SCK, MISO, and MOSI on Crossbar 1.

1 (ENABLED): Enable SPI1 SCK, MISO, and MOSI on Crossbar 1.
SPI1NSSEN

SPI1 NSS Pin Enable.

0 (DISABLED): Disable SPI1 NSS on Crossbar 1.

1 (ENABLED): Enable SPI1 NSS on Crossbar 1.
RTC0EN

RTC0 Output Enable.

0 (DISABLED): Disable RTC0 Output on Crossbar 1.

1 (ENABLED): Enable RTC0 Output on Crossbar 1.
SPI2EN

SPI2 Enable.

0 (DISABLED): Disable SPI2 SCK, MISO, and MOSI on Crossbar 1.

1 (ENABLED): Enable SPI2 SCK, MISO, and MOSI on Crossbar 1.
SPI2NSSEN

SPI2 NSS Pin Enable.

0 (DISABLED): Disable SPI2 NSS on Crossbar 1.

1 (ENABLED): Enable SPI2 NSS on Crossbar 1.
USART1EN

USART1 Enable.

0 (DISABLED): Disable USART1 RX and TX on Crossbar 1.

1 (ENABLED): Enable USART1 RX and TX on Crossbar 1.
USART1FCEN

USART1 Flow Control Enable.

0 (DISABLED): Disable USART1 flow control on Crossbar 1.

1 (ENABLED): Enable USART1 flow control on Crossbar 1.
USART1CEN

USART1 Clock Signal Enable.

0 (DISABLED): Disable USART1 clock on Crossbar 1.

1 (ENABLED): Enable USART1 clock on Crossbar 1.
UART0EN

UART0 Enable.

0 (DISABLED): Disable UART0 RX and TX on Crossbar 1.

1 (ENABLED): Enable UART0 RX and TX on Crossbar 1.
UART0FCEN

UART0 Flow Control Enable.

0 (DISABLED): Disable UART0 flow control on Crossbar 1.

1 (ENABLED): Enable UART0 flow control on Crossbar1.
I2S0TXEN

I2S0 TX Enable.

0 (DISABLED): Disable I2S0 TX on Crossbar 1.

1 (ENABLED): Enable I2S0 TX on Crossbar 1.
I2C0EN

I2C0 Enable.

0 (DISABLED): Disable I2C0 SDA and SCL on Crossbar 1.

1 (ENABLED): Enable I2C0 SDA and SCL on Crossbar 1.
UART1EN

UART1 Enable.

0 (DISABLED): Disable UART1 RX and TX on Crossbar 1.

1 (ENABLED): Enable UART1 RX and TX on Crossbar 1.
I2S0RXEN

I2S0 RX Enable.

0 (DISABLED): Disable I2S0 RX on Crossbar 1.

1 (ENABLED): Enable I2S0 RX on Crossbar 1.
LPT0OEN

LPTIMER0 Output Enable.

0 (DISABLED): Disable LPTIMER0 Output on Crossbar 1.

1 (ENABLED): Enable LPTIMER0 Output on Crossbar 1.
I2C1EN

I2C1 Enable.

0 (DISABLED): Disable I2C1 SDA and SCL on Crossbar 1.

1 (ENABLED): Enable I2C1 SDA and SCL on Crossbar 1.
KILLHDEN

High Drive Kill Pin Enable.

0 (DISABLED): Disable the PB High Drive Kill Pin on Crossbar 1.

1 (ENABLED): Enable the PB High Drive Kill Pin on Crossbar 1.
XBAR1EN

Crossbar 1 Enable.

0 (DISABLED): Disable Crossbar 1.

1 (ENABLED): Enable Crossbar 1.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data